A semiconductor storage device, including memory cells at the points of intersection of word lines and bit lines, arranged at right angles thereto, is finding widespread use in many fields of applications. With this semiconductor storage device, a negative word line system, in which the ‘floating’ of the VBB level of the negative potential at the time of resetting the word line is suppressed to diminish the leakage current of, e.g., the memory cell, has been known and disclosed in, e.g., Patent Publication 1. In the word line driving circuit of the Patent Document 1, the voltage on the word line is pulled down to the potential VSS (ground potential), after which the word line voltage is lowered to VBB (negative potential) that is lower than VSS over a certain time delay. This preset time delay is generated by a delay circuit in a signal generating circuit adapted for generating a word line driving signal.
It is also possible to suppress the consumption of the VPP potential, at the time of activation of the word line, in the same manner as the case where the ‘float’ of the VBB level is suppressed at the time of resetting the word line. It is known that the VPP, as the boost-up power supply, is generated within the DRAM, by exploiting a charge pumping system from the power supply VDD. Hence, the following equation:IVPP=α*IVDDwhere IVPP is the current consumption of VPP, IVDD is the current consumption of VDD and α is a constant, may be obtained. From the equation, reduction of IVPP has a marked effect in decreasing the current consumption IVDD of the DRAM itself.[Patent Document 1]
JP Patent Kokai Publication No. JP-A-10-241361 (FIGS. 3, 5 and 8)